1. Field
The present invention relates to a data storage system which is applied to a computer system, that includes volatile (e.g. SRAM, SDRAM) and non-volatile (e.g. flash memory, mechanical hard disk) storage components.
2. Description of the Related Art
In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore can be completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache data transfer is handled by one DMA engine and another DMA engine for cache-to-IO bus data transfer. To start the transfer, the processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. While the first data buffer in the cache is being drained, another data buffer can be filled concurrently in memory. The data transfer continues in this fashion, two DMA engines operating in parallel utilizing multiple data buffer spaces in the cache. Notice that in between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. Note that each of the transfers, memory-to-cache and cache-to-IC, can also be handled using two or more DMA engines; either DMA engines are used sequentially or simultaneously.